CRC Control Registers
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SPNU563A–March 2018
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Cyclic Redundancy Check (CRC) Controller Module
18.4.25 CRC Channel 2 Watchdog Timeout Preload Register A (CRC_WDTOPLD2)
Figure 18-33. CRC Channel 2 Watchdog Timeout Preload Register A (CRC_WDTOPLD2)
[offset = 8Ch]
31 24 23 16
Reserved CRC_WDTOPLD2
R-0 R/W-0
15 0
CRC_WDTOPLD2
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-29. CRC Channel 2 Watchdog Timeout Preload Register A (CRC_WDTOPLD2)
Field Descriptions
Bit Field Value Description
31-24 Reserved 0 Reads return 0. Writes have no effect.
23-0 CRC_WDTOPLD2 Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of
clock cycles within which the DMA must transfer the next block of data patterns. In Semi-CPU
mode, this register is used to indicate the sector number for which the compression complete
has last happened.
18.4.26 CRC Channel 2 Block Complete Timeout Preload Register B (CRC_BCTOPLD2)
Figure 18-34. CRC Channel 2 Block Complete Timeout Preload Register B (CRC_BCTOPLD2)
[offset = 90h]
31 24 23 16
Reserved CRC_BCTOPLD2
R-0 R/W-0
15 0
CRC_BCTOPLD2
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-30. CRC Channel 2 Block Complete Timeout Preload Register B (CRC_BCTOPLD2)
Field Descriptions
Bit Field Value Description
31-24 Reserved 0 Reads return 0. Writes have no effect.
23-0 CRC_BCTOPLD2 Channel 2 Block Complete Timeout Counter Preload Register. This register contains the
number of clock cycles within which the CRC for an entire block needs to complete before a
timeout interrupt is generated.
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