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ESM Control Registers
569
SPNU563A–March 2018
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Error Signaling Module (ESM)
16.4.7 ESM Status Register 1 (ESMSR1)
This register is dedicated for Group1 Channel[31:0]. Note that the ESMSR1 status register will get
updated if an error condition occurs, regardless if the corresponding interrupt enable flag is set or not.
Figure 16-17. ESM Status Register 1 (ESMSR1) [offset = 18h]
31 16
ESF[31:16]
R/W1CP-X/0
15 0
ESF[15:0]
R/W1CP-X/0
LEGEND: R/W = Read/Write; W1CP = Write 1 to clear in privilege mode only; -n = value after reset/PORRST; X = value is unchanged
Table 16-9. ESM Status Register 1 (ESMSR1) Field Descriptions
Bit Field Value Description
31-0 ESF Error Status Flag. Provides status information on a pending error.
Read in User and Privileged mode. Write in Privileged mode only.
0 Read: No error occurred; no interrupt is pending.
Write: Leaves the bit unchanged.
1 Read: Error occurred; interrupt is pending.
Write: Clears the bit.
Note: After RST, if one of these flags are set and the corresponding interrupt are enabled, the
interrupt service routine will be called.
16.4.8 ESM Status Register 2 (ESMSR2)
This register is dedicated for Group2.
Figure 16-18. ESM Status Register 2 (ESMSR2) [offset = 1Ch]
31 16
ESF2[31:16]
R/W1CP-0
15 0
ESF2[15:0]
R/W1CP-0
LEGEND: R/W = Read/Write; W1CP = Write 1 to clear in privilege mode only; -n = value after reset
Table 16-10. ESM Status Register 2 (ESMSR2) Field Descriptions
Bit Field Value Description
31-0 ESF2 Error Status Flag. Provides status information on a pending error.
Read in User and Privileged mode. Write in Privileged mode only.
0 Read: No error occurred; no interrupt is pending.
Write: Leaves the bit unchanged.
1 Read: Error occurred; interrupt is pending.
Write: Clears the bit. ESMSSR2 is not impacted by this action.
Note: In normal operation the flag gets cleared when reading the appropriate vector in the
ESMIOFFHR offset register. Reading ESMIOFFHR will not clear the ESMSR1 and the shadow
register ESMSSR2.