www.ti.com
DCC Control Registers
551
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Dual-Clock Comparator (DCC) Module
15.4.2 DCC Revision Id Register (DCCREV)
Figure 15-8 and Table 15-3 describe the DCC Revision Id register.
Figure 15-8. DCC Revision Id Register (DCCREV) [offset = 4h]
31 30 29 28 27 16
SCHEME Reserved FUNC
R-01 R-0 R-0
15 11 10 8 7 6 5 0
RTL MAJOR CUSTOM MINOR
R-0 R-2h R-0 R-4h
LEGEND: R = Read only; -n = value after reset
Table 15-3. DCC Revision Id Register (DCCREV) Field Descriptions
Bit Field Value Description
31-30 SCHEME 01 Reads return 01, writes have no effect.
29-28 Reserved 0 Reads return 0. Writes have no effect.
27-16 FUNC 0 Functional release number. Reads return 0x000, writes have no effect.
15-11 RTL 0 Design release number. Reads return 0x00, writes have no effect.
10-8 MAJOR 2h Major revision number. Reads return 0x2, writes have no effect.
7-6 CUSTOM 0 Custom version number. Reads return 0x0, writes have no effect.
5-0 MINOR 4h Minor revision number. Reads return 0x4, writes have no effect.
15.4.3 DCC Counter0 Seed Register (DCCCNT0SEED)
Figure 15-9 and Table 15-4 describe the DCC Counter0 Seed register.
Figure 15-9. DCC Counter0 Seed Register (DCCCNT0SEED) [offset = 8h]
31 20 19 16
Reserved COUNT0 SEED
R-0 R/WP-0
15 0
COUNT0 SEED
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 15-4. DCC Counter0 Seed Register (DCCCNT0SEED) Field Descriptions
Bit Field Value Description
31-20 Reserved 0 Reads return 0. Writes have no effect.
19-0 COUNT0 SEED Seed value for DCC counter0.
Reads in any operating mode return the current value of counter0.
Writing in privileged mode only sets the current seed value for counter0.
NOTE: Seed for Counter0 must be non-zero
The DCC must only be enabled after programming a non-zero value in the COUNT0 SEED
register.
To Next Page
Loading...
Need help?
General
