DCAN Control Registers
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SPNU563A–March 2018
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Controller Area Network (DCAN) Module
27.17.19 Interrupt Pending Registers (DCAN INTPND12 to DCAN INTPND78)
These registers hold the IntPnd bits of the implemented message objects. By reading out these bits, the
CPU can check for pending interrupts in the message objects. The IntPnd bit of a specific message object
can be set/reset by the CPU via the IF1/IF2 Interface Register sets, or by the Message Handler after a
reception or a successful transmission.
Figure 27-44. Interrupt Pending 12 Register (DCAN INTPND12) [offset = B0h]
31 0
IntPnd[32:1]
R-0
LEGEND: R = Read only; -n = value after reset
Figure 27-45. Interrupt Pending 34 Register (DCAN INTPND34) [offset = B4h]
31 0
IntPnd[64:33]
R-0
LEGEND: R = Read only; -n = value after reset
Figure 27-46. Interrupt Pending 56 Register (DCAN INTPND56) [offset = B8h]
31 0
IntPnd[96:65]
R-0
LEGEND: R = Read only; -n = value after reset
Figure 27-47. Interrupt Pending 78 Register (DCAN INTPND78) [offset = BCh]
31 0
IntPnd[128:97]
R-0
LEGEND: R = Read only; -n = value after reset
Table 27-22. Interrupt Pending Registers Field Descriptions
Bit Name Value Description
31-0 IntPnd[128:1] Interrupt Pending Bits (for all message objects).
0 This message object is not the source of an interrupt.
1 This message object is the source of an interrupt.
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