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Flash Control Registers
367
SPNU563A–March 2018
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F021 Level 2 Flash Module Controller (L2FMC)
7.10.15 Flash Bank/Pump Ready Register (FBPRDY)
FBPRDY register allows you to determine if the pump and banks are ready for performing a read access.
Figure 7-25. Flash Bank/Pump Ready Register (FBPRDY) (offset = 44h)
31 24 23 22 18 17 16
Reserved BANKBUSY[7] Reserved BANKBUSY[1:0]
R-0 R-0 R-1 R-0
15 14 8 7 6 2 1 0
PUMPRDY Reserved BANKRDY[7] Reserved BANKRDY[1:0]
R-1 R-0 R-1 R-0 R-1
LEGEND: R = Read only; -n = value after reset
Table 7-27. Flash Bank/Pump Ready Register (FBPRDY) Register Description
Bit Field Value Description
31-24 Reserved 0 Reads return 0. Writes have no effect.
23 BANKBUSY[7] Bank 7 Busy Status
0 Bank is not busy with any FSM or CPU operation.
1 Bank is busy with an FSM or CPU operation.
22-18 Reserved 1 Reads return 1. Writes have no effect.
17-16 BANKBUSY[1:0] Bank 0 (bit 16) and Bank 1 (bit 17) Busy Status
0 Bank is not busy with any FSM or CPU operation.
1 Bank is busy with an FSM or CPU operation.
15 PUMPRDY Pump Ready is a read-only bit which allows software to determine if the pump is ready for Flash
access before attempting the actual access. When set, it means that the charge pump is in active
power state. If an access is made to a bank which is not ready then wait states are asserted until it
becomes ready
0 Pump is not ready.
1 Pump is ready.
14-8 Reserved 0 Reads return 0. Writes have no effect.
7 BANKRDY[7] Bank 7 Ready Status
0 Bank is not ready for Flash access.
1 Bank is ready for Flash access.
6-2 Reserved 0 Reads return 0. Writes have no effect.
1-0 BANKRDY[1:0] Bank 0 (bit 0) and Bank 1 (bit 1) Ready Status
0 Bank is not ready for Flash access.
1 Bank is ready for Flash access.
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