EMIF Module Architecture
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SPNU563A–March 2018
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External Memory Interface (EMIF)
21.2.14 System Considerations
This section describes various system considerations to keep in mind when operating the EMIF.
21.2.14.1 Asynchronous Request Times
In a system that interfaces to both SDRAM and asynchronous memory, the asynchronous requests must
not take longer than the smaller of the following two values:
• t
RAS
(typically 120 μs) - to avoid violating the maximum time allowed between issuing an ACTV and
PRE command to the SDRAM.
• t
Refresh Rate
× 11 (typically 15.7 μs × 11 = 172.7 μs) - to avoid refresh violations on the SDRAM.
The length of an asynchronous request is controlled by multiple factors, the primary factor being the
number of access cycles required to complete the request. For example, an asynchronous request for
4 bytes will require four access cycles using an 8-bit data bus and only two access cycle using a 16-bit
data bus. The maximum request size that the EMIF can be sent is 16 words, therefore the maximum
number of access cycles per memory request is 64 when the EMIF is configured with an 8-bit data
bus. The length of the individual access cycles that make up the asynchronous request is determined
by the programmed setup, strobe, hold, and turnaround values, but can also be extended with the
assertion of the EMIF_nWAIT input signal up to a programmed maximum limit. It is up to the user to
make sure that an entire asynchronous request does not exceed the timing values listed above when
also interfacing to an SDRAM device. This can be done by limiting the asynchronous timing
parameters.
21.2.14.2 Interface to External Peripheral or FIFO Memory
If EMIF is used to interface to an external peripheral or FIFO logic (for example, UHPI), it is recommended
to use the host CPU's Memory Protection Unit (MPU) to define this external memory range as a region
that is either strongly-ordered or of device type.
21.2.14.3 Interface to External SDRAM
If EMIF is used to interface to an external SDRAM, it is recommended to burst as much as possible to
normal memory to improve the interface bandwidth.
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