Texas Instruments TMS570LC4357

PBIST Control Registers www.ti.com
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SPNU563A–March 2018
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Programmable Built-In Self-Test (PBIST) Module
9.5.6 Fail Status Fail Register (FSRF0)
This register indicates if a failure occurred during a memory self-test. Bit [0] gets set whenever a failure
occurs. Figure 9-8 and Table 9-7 illustrate the FSRF0 register.
Figure 9-8. Fail Status Fail Register 0 (FSRF0) [offset = 0190h]
31 16
Reserved
R-0
15 1 0
Reserved FSRF0
R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-7. Fail Status Fail Register 0 (FSRF0) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Reads return 0. Writes have no effect.
0 FSRF0 Fail Status 0. This bit would be cleared by reset of the module using MSTGCR register in system
module.
0 No failure occurred.
1 Failure occurred on port 0.