Memory Organization
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SPNU563A–March 2018
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Architecture
2.2 Memory Organization
2.2.1 Memory-Map Overview
The Cortex-R5F uses a 32-bit address bus, giving it access to a memory space of 4GB. This space is
divided into several regions, each addressed by different memory selects. Figure 2-3 shows the memory-
map of the microcontroller.
The main flash instruction memory is addressed starting at 0x00000000 by default. This is also the reset
vector location – the ARM Cortex-R5F processor core starts execution from the reset vector address of
0x00000000 whenever the core gets reset.
The CPU data RAM is addressed starting at 0x08000000 by default.
The device also supports the swapping of the CPU instruction memory (flash) and data memory (RAM).
This can be done by configuring the MEM SWAP field of the Bus Matrix Module Control Register 1
(BMMCR1).
After swapping, the data RAM is accessed starting from 0x00000000 and the RAM ECC locations are
accessed starting from 0x00400000. The flash memory is now accessed starting from 0x08000000.
NOTE: After the swap with the flash memory-mapped to 0x08000000, only 512kB of the flash
memory from 0x08000000 to 0x0807FFFF will be accessible by the bus masters.
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