Texas Instruments TMS570LC4357

www.ti.com Clocks
145
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Architecture
2.4.3 Low Power Modes
All clock domains are active in the normal operating mode. This is the default mode of operation. As
described in Section 2.4.1.1 and Section 2.4.2.1, the application can choose to disable any particular clock
source and domain that it does not plan to use. Also, the peripheral central resource controller (PCR) has
control registers to enable / disable the peripheral clock (VCLK) for each peripheral select. This offers the
application a large number of choices for enabling / disabling clock sources, or clock domains, or clocks to
specific peripherals.
This section describes three particular low-power modes and their typical characteristics. They are not the
only low-power modes configurable by the application, as just described.
Table 2-11. Typical Low-Power Modes
Mode
Name
Active Clock
Source(s)
Active
Clock
Domain(s)
Wake Up Options
Suggested
Wake Up
Clock
Source(s)
Wake Up Time(wake up detected -to- CPU
code execution start)
Doze Main oscillator RTICLK1
RTI interrupt,
GIO interrupt,
CAN message,
SCI message
Main oscillator
Flash pump sleep -> active transition time
+
Flash bank sleep -> standby transition time
+
Flash bank standby -> active transition time
Snooze LF LPO RTICLK1
RTI interrupt,
GIO interrupt,
CAN message,
SCI message
HF LPO
HF LPO warm start-up time
+
Flash pump sleep -> active transition time
+
Flash bank sleep -> standby transition time
+
Flash bank standby -> active transition time
Sleep None None
GIO interrupt,
CAN message,
SCI message
HF LPO
HF LPO warm start-up time
+
Flash pump sleep -> active transition time
+
Flash bank sleep -> standby transition time
+
Flash bank standby -> active transition time