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SDC MMR Registers
273
SPNU563A–March 2018
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4.4.1 SDC Status Register (SDC_STATUS)
Figure 4-2. SDC Status Register (SDC_STATUS) (offset = 00h)
31 16
Reserved
R-0
15 5 4 3 2 1 0
GLOBAL_ERROR NT_OK NT_RUN PT_OK PT_RUN
R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 4-6. SDC Status Register (SDC_STATUS) Field Descriptions
Bit Field Value Description
31-5 Reserved 0 Reads return 0 and writes have no effect.
4 GLOBAL_ERROR This bit indicates that one safety diagnostic checker has asserted an error input that is
captured in error log registers located at address offset from 0x08 to 0x28.
0 No error is detected by any checker.
1 Error is detected by one checker. To find out the type of error from which checker, read the
error log registers located at address offset from 0x08 to 0x28.
3 NT_OK Negative test OK status for self-test.
0 Negative test has failed.
1 Negative test has passed.
2 NT_RUN Negative test on-going status.
0 Negative test has ended.
1 Negative test is on-going.
1 PT_OK Positive test OK status for self-test.
0 Positive test has failed.
1 Positive test has passed.
0 PT_RUN Positive test on-going status.
0 Positive test has ended.
1 Positive test is on-going.
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