Texas Instruments TMS570LC4357 User Manual

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SPNU563A–March 2018
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Self-Test Controller (STC) Module
10.8.8 CORE1 Current MISR Registers (CORE1_CURMISR[3:0])
This register is described in Figure 10-15 through Figure 10-18 and Table 10-16.
NOTE: This register gets reset to its default value with power-on or system reset assertion.
Figure 10-15. CORE1 Current MISR Register (CORE1_CURMISR3) [offset = 1Ch]
31 16
MISR[31:16]
R-0
15 0
MISR[15:0]
R-0
LEGEND: R = Read only; -n = value after reset
Figure 10-16. CORE1 Current MISR Register (CORE1_CURMISR2) [offset = 20h]
31 16
MISR[63:48]
R-0
15 0
MISR[47:32]
R-0
LEGEND: R = Read only; -n = value after reset
Figure 10-17. CORE1 Current MISR Register (CORE1_CURMISR1) [offset = 24h]
31 16
MISR[95:80]
R-0
15 0
MISR[79:64]
R-0
LEGEND: R = Read only; -n = value after reset
Figure 10-18. CORE1 Current MISR Register (CORE1_CURMISR0) [offset = 28h]
31 16
MISR[127:112]
R-0
15 0
MISR[111:96]
R-0
LEGEND: R = Read only; -n = value after reset
Table 10-16. CORE1 Current MISR Register (CORE1_CURMISRn) Field Descriptions
Bit Field Description
127-0 MISR MISR data from CORE1
This register contains the MISR data from the CORE1 for the most recent interval in case of segment 0 and all
other segments. This value is compared with the GOLDEN MISR value copied from ROM.

Texas Instruments TMS570LC4357 Specifications

General

Brand	Texas Instruments
Model	TMS570LC4357
Category	Microcontrollers
Language	English