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RTI Control Registers
595
SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
Real-Time Interrupt (RTI) Module
17.3 RTI Control Registers
Table 17-1 provides a summary of the registers. The registers support 8-bit, 16-bit, and 32-bit writes. The
offset is relative to the associated peripheral select. See the following sections for detailed descriptions of
the registers. The base address for the control registers is FFFF FC00h. The address locations not listed
are reserved.
Table 17-1. RTI Registers
Offset Acronym Register Description Section
00h RTIGCTRL RTI Global Control Register Section 17.3.1
04h RTITBCTRL RTI Timebase Control Register Section 17.3.2
08h RTICAPCTRL RTI Capture Control Register Section 17.3.3
0Ch RTICOMPCTRL RTI Compare Control Register Section 17.3.4
10h RTIFRC0 RTI Free Running Counter 0 Register Section 17.3.5
14h RTIUC0 RTI Up Counter 0 Register Section 17.3.6
18h RTICPUC0 RTI Compare Up Counter 0 Register Section 17.3.7
20h RTICAFRC0 RTI Capture Free Running Counter 0 Register Section 17.3.8
24h RTICAUC0 RTI Capture Up Counter 0 Register Section 17.3.9
30h RTIFRC1 RTI Free Running Counter 1 Register Section 17.3.10
34h RTIUC1 RTI Up Counter 1 Register Section 17.3.11
38h RTICPUC1 RTI Compare Up Counter 1 Register Section 17.3.12
40h RTICAFRC1 RTI Capture Free Running Counter 1 Register Section 17.3.13
44h RTICAUC1 RTI Capture Up Counter 1 Register Section 17.3.14
50h RTICOMP0 RTI Compare 0 Register Section 17.3.15
54h RTIUDCP0 RTI Update Compare 0 Register Section 17.3.16
58h RTICOMP1 RTI Compare 1 Register Section 17.3.17
5Ch RTIUDCP1 RTI Update Compare 1 Register Section 17.3.18
60h RTICOMP2 RTI Compare 2 Register Section 17.3.19
64h RTIUDCP2 RTI Update Compare 2 Register Section 17.3.20
68h RTICOMP3 RTI Compare 3 Register Section 17.3.21
6Ch RTIUDCP3 RTI Update Compare 3 Register Section 17.3.22
70h RTITBLCOMP RTI Timebase Low Compare Register Section 17.3.23
74h RTITBHCOMP RTI Timebase High Compare Register Section 17.3.24
80h RTISETINTENA RTI Set Interrupt Enable Register Section 17.3.25
84h RTICLEARINTENA RTI Clear Interrupt Enable Register Section 17.3.26
88h RTIINTFLAG RTI Interrupt Flag Register Section 17.3.27
90h RTIDWDCTRL Digital Watchdog Control Register Section 17.3.28
94h RTIDWDPRLD Digital Watchdog Preload Register Section 17.3.29
98h RTIWDSTATUS Watchdog Status Register Section 17.3.30
9Ch RTIWDKEY RTI Watchdog Key Register Section 17.3.31
A0h RTIDWDCNTR RTI Digital Watchdog Down Counter Register Section 17.3.32
A4h RTIWWDRXNCTRL Digital Windowed Watchdog Reaction Control Register Section 17.3.33
A8h RTIWWDSIZECTRL Digital Windowed Watchdog Window Size Control Register Section 17.3.34
ACh RTIINTCLRENABLE RTI Compare Interrupt Clear Enable Register Section 17.3.35
B0h RTICOMP0CLR RTI Compare 0 Clear Register Section 17.3.36
B4h RTICOMP1CLR RTI Compare 1 Clear Register Section 17.3.37
B8h RTICOMP2CLR RTI Compare 2 Clear Register Section 17.3.38
BCh RTICOMP3CLR RTI Compare 3 Clear Register Section 17.3.39
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