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RTI Control Registers
599
SPNU563A–March 2018
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Real-Time Interrupt (RTI) Module
17.3.4 RTI Compare Control Register (RTICOMPCTRL)
The compare control register controls the source for the compare registers. This register is shown in
Figure 17-15 and described in Table 17-5.
Figure 17-15. RTI Compare Control Register (RTICOMPCTRL) [offset = 0Ch]
31 16
Reserved
R-0
15 13 12 11 9 8
Reserved COMPSEL3 Reserved COMPSEL2
R-0 R/WP-0 R-0 R/WP-0
7 5 4 3 1 0
Reserved COMPSEL1 Reserved COMPSEL0
R-0 R/WP-0 R-0 R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 17-5. RTI Compare Control Register (RTICOMPCTRL) Field Descriptions
Bit Field Value Description
31-13 Reserved 0 Reads return 0. Writes have no effect.
12 COMPSEL3 Compare select 3. This bit determines the counter with which the compare value held in compare
register 3 (RTICOMP3) is compared.
0 Value will be compared with RTIFRC0.
1 Value will be compared with RTIFRC1.
11-9 Reserved 0 Reads return 0. Writes have no effect.
8 COMPSEL2 Compare select 2. This bit determines the counter with which the compare value held in compare
register 2 (RTICOMP2) is compared.
0 Value will be compared with RTIFRC0.
1 Value will be compared with RTIFRC1.
7-5 Reserved 0 Reads return 0. Writes have no effect.
4 COMPSEL1 Compare select 1. This bit determines the counter with which the compare value held in compare
register 1 (RTICOMP1) is compared.
0 Value will be compared with RTIFRC0.
1 Value will be compared with RTIFRC1.
3-1 Reserved 0 Reads return 0. Writes have no effect.
0 COMPSEL0 Compare select 0. This bit determines the counter with which the compare value held in compare
register 0 (RTICOMP0) is compared.
0 Value will be compared with RTIFRC0.
1 Value will be compared with RTIFRC1.
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