Memory Organization
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SPNU563A–March 2018
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Architecture
2.2.4 On-Chip SRAM
Several SRAM modules are implemented on the device to support the functionality of the modules
included.
Reads from both the level 1 and level 2 SRAM are protected by ECC calculated inside the CPU. Reads
from all other memories are protected by either the parity with configurable odd or even parity scheme or
ECC that is evaluated in parallel with the actual read.
The TMS570LC43x microcontrollers are targeted towards safety-critical applications, and it is critical for
any failures in the on-chip SRAM modules to be identified before these modules are used for safety-critical
functions. These microcontrollers support a Programmable Built-In Self-Test (PBIST) mechanism that is
used to test each on-chip SRAM module for faults. The PBIST is usually run on device start-up as it is a
destructive test and all contents of the tested SRAM module are overwritten during the test.
The microcontrollers also support a hardware-based auto-initialization of on-chip SRAM modules. This
process also takes into account the read protection scheme implemented for each SRAM module – ECC
or parity.
TI recommends that the PBIST routines be executed on the SRAM modules prior to the auto-initialization.
The following sections describe these two processes.
2.2.4.1 PBIST RAM Grouping and Algorithm Mapping For On-Chip SRAM Modules
Table 2-5 shows the groupings of the various on-chip memories for PBIST. It also lists the memory types
and their assigned RAM Group Select (RGS) and Return Data Select (RDS). Refer to the PBIST chapter
for more details on the usage of the RGS and RDS information.
Table 2-5. PBIST Memory Grouping
Module RAM Group # RGS RDS Memory Type
PBIST_ROM 1 1 1 ROM
STC1_1_ROM_R5 2 14 1 ROM
STC1_2_ROM_R5 3 14 2 ROM
STC2_ROM_N2HET 4 15 1 ROM
AWM1 5 2 1 Two-port
DCAN1 6 3 1 to 6 Two-port
DCAN2 7 4 1 to 6 Two-port
DMA 8 5 1 to 6 Two-port
HTU1 9 6 1 to 6 Two-port
MIBSPI1 10 8 1 to 4 Two-port
MIBSPI2 11 9 1 to 4 Two-port
MIBSPI3 12 10 1 to 4 Two-port
N2HET1 13 11 1 to 12 Two-port
VIM 14 12 1, 2 Two-port
Reserved 15 13 1, 2 Two-port
RTP 16 16 1 to 12 Two-port
ATB 17 17 1 to 16 Two-port
AWM2 18 18 1 Two-port
DCAN3 19 19 1 to 6 Two-port
DCAN4 20 20 1 to 6 Two-port
HTU2 21 21 1 to 6 Two-port
MIBSPI4 22 22 1 to 4 Two-port
MIBSPI5 23 23 1 to 4 Two-port
N2HET2 24 24 1 to 12 Two-port
FTU 25 25 1 Two-port
FRAY_INBUF_OUTBUF 26 26 1 to 8 Two-port
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