Texas Instruments TMS570LC4357 User Manual

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SPNU563A–March 2018
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Architecture
Table 2-4. EPC Registers Bit Mapping
Address
Offset
Register Name Bit # Error Source Remark
8h UERRSTAT
0
Uncorrectable ECC for
DMA interface
• Bit associates with the Uncorrectable ECC error
detected by the CPU Interconnect Subsystem
for the DMA interface
• See Interconnect chapter for details on the
ECC generation and evaluation for DMA
interface
1
Uncorrectable ECC for
PS_SCR_M interface
• Bit associates with the Uncorrectable ECC error
detected by the CPU Interconnect Subsystem
for the PS_SCR_M interface
• See Interconnect chapter for details on the
ECC generation and evaluation for DMA
interface
10h FIFOFULLSTAT
0 CPU Correctable ECC error
• Bit associates with the FIFO full status for the
interface that is used to capture the CPU
correctable error event
• Correctable error event exported by CPU's
event bus.
1 Reserved
2
Correctable ECC for
DMA interface
• Bit associates with the FIFO full status for the
interface that is used to capture the DMA
correctable error event
• Correctable error event detected by the CPU
Interconnect Subsystem for the DMA PortA
interface.
3
Correctable ECC for
PS_SCR_M interface
• Bit associates with the FIFO full status for the
interface that is used to capture the
PS_SCR_M correctable error event
• Correctable error event detected by the CPU
Interconnect Subsystem for the PS_SCR_M
interface.
4
Correctable ECC error from L2
SRAM
• Bit associates with the FIFO full status for the
interface that is used to capture the L2 SRAM
correctable error event
• Correctable error event detected by the L2
SRAM wrapper during the read phase of a
Read-Modify-Write operation due to a less than
64-bit write from the bus master.
14h OVRFLWSTAT
0 CPU Correctable ECC error
• Bit associates with the FIFO overflow status for
the interface that is used to capture the CPU
correctable error event
1 Reserved
2
Correctable ECC for
DMA interface
• Bit associates with the FIFO overflow status for
the interface that is used to capture the DMA
correctable error event
3
Correctable ECC for
PS_SCR_M interface
• Bit associates with the FIFO overflow status for
the interface that is used to capture the
PS_SCR_M correctable error event
4
Correctable ECC error from L2
SRAM
• Bit associates with the FIFO overflow status for
the interface that is used to capture the L2
SRAM correctable error event
20h UERRADDR0 31:0
Uncorrectable ECC for
DMA interface
• Uncorrectable error address register for the
DMA interface
24h UERRADDR1 31:0
Uncorrectable ECC for
PS_SCR_M interface
• Uncorrectable error address register for the
PS_SCR_M interface

Texas Instruments TMS570LC4357 Specifications

General

Brand	Texas Instruments
Model	TMS570LC4357
Category	Microcontrollers
Language	English