Texas Instruments TMS570LC4357

www.ti.com ESM Control Registers
575
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Error Signaling Module (ESM)
16.4.17 ESM Influence ERROR Pin Set/Status Register 4 (ESMIEPSR4)
This register is dedicated for Group1 Channel[63:32].
Figure 16-27. ESM Influence ERROR Pin Set/Status Register 4 (ESMIEPSR4) [offset = 40h]
31 16
IEPSET[63:48]
R/WP-0
15 0
IEPSET[47:32]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 16-19. ESM Influence ERROR Pin Set/Status Register 4 (ESMIEPSR4) Field Descriptions
Bit Field Value Description
63-32 IEPSET Set influence on ERROR pin.
Read in User and Privileged mode. Write in Privileged mode only.
0 Read: Failure on channel x has no influence on ERROR pin.
Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR4 register unchanged.
1 Read: Failure on channel x has influence on ERROR pin.
Write: Enables failure influence on ERROR pin and sets the corresponding clear bit in the
ESMIEPCR4 register.
16.4.18 ESM Influence ERROR Pin Clear/Status Register 4 (ESMIEPCR4)
This register is dedicated for Group1 Channel[63:32].
Figure 16-28. ESM Influence ERROR Pin Clear/Status Register 4 (ESMIEPCR4) [offset = 44h]
31 16
IEPCLR[63:48]
R/WP-0
15 0
IEPCLR[47:32]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 16-20. ESM Influence ERROR Pin Clear/Status Register 4 (ESMIEPCR4) Field Descriptions
Bit Field Value Description
63-32 IEPCLR Clear influence on ERROR pin.
Read in User and Privileged mode. Write in Privileged mode only.
0 Read: Failure on channel x has no influence on ERROR pin.
Write: Leaves the bit and the corresponding clear bit in the ESMIEPSR4 register unchanged.
1 Read: Failure on channel x has influence on ERROR pin.
Write: Disables failure influence on ERROR pin and clears the corresponding clear bit in the
ESMIEPSR4 register.