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EMIF Registers
831
SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
External Memory Interface (EMIF)
Table 21-27. SDRAM Configuration Register (SDCR) Field Descriptions (continued)
Bit Field Value Description
11-9 CL CAS Latency. This field defines the CAS latency to be used when accessing connected SDRAM
devices. A 1 must be simultaneously written to the BIT11_9LOCK bit field of this register in order to
write to the CL bit field. Writing to this field triggers the SDRAM initialization sequence.
0-1h Reserved
2h CAS latency = 2 EMIF_CLK cycles
3h CAS latency = 3 EMIF_CLK cycles
4h-7h Reserved
8 BIT11_9LOCK Bits 11 to 9 lock. CL can only be written if BIT11_9LOCK is simultaneously written with a 1.
BIT11_9LOCK is always read as 0. Writing to this field triggers the SDRAM initialization sequence.
0 CL cannot be written.
1 CL can be written.
7 Reserved 0 Reserved. The reserved bit location is always read as 0. If writing to this field, always write the
default value of 0.
6-4 IBANK Internal SDRAM Bank size. This field defines number of banks inside the connected SDRAM
devices. Writing to this field triggers the SDRAM initialization sequence.
0 1 bank SDRAM devices.
1 2 bank SDRAM devices.
2 4 bank SDRAM devices.
3h-7h Reserved.
3 Reserved 0 Reserved. The reserved bit location is always read as 0. If writing to this field, always write the
default value of 0.
2-0 PAGESIZE Page Size. This field defines the internal page size of connected SDRAM devices. Writing to this
field triggers the SDRAM initialization sequence.
0 8 column address bits (256 elements per row)
1h 9 column address bits (512 elements per row)
2h 10 column address bits (1024 elements per row)
3h 11 column address bits (2048 elements per row)
4h-7h Reserved
21.3.4 SDRAM Refresh Control Register (SDRCR)
The SDRAM refresh control register (SDRCR) is used to configure the rate at which connected SDRAM
devices will be automatically refreshed by the EMIF. Refer to Section 21.2.5.6 on the refresh controller for
more details. The SDRCR is shown in Figure 21-18 and described in Table 21-28.
Figure 21-18. SDRAM Refresh Control Register (SDRCR) [offset = 0Ch]
31 16
Reserved
R-0
15 13 12 0
Reserved RR
R-0 R/W-80h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21-28. SDRAM Refresh Control Register (SDRCR) Field Descriptions
Bit Field Value Description
31-13 Reserved 0 Reserved. The reserved bit location is always read as 0. If writing to this field, always write the
default value of 0.
12-0 RR 0-1FFFh Refresh Rate. This field is used to define the SDRAM refresh period in terms of EMIF_CLK cycles.
Writing a value < 0x0020 to this field will cause it to be loaded with (2 × T_RFC) + 1 value from the
SDRAM timing register (SDTIMR).
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