Texas Instruments TMS570LC4357

N2HET Control Registers www.ti.com
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SPNU563A–March 2018
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High-End Timer (N2HET) Module
23.4.27 Parity Address Register (HETPAR)
N2HET1: offset = FFF7 B878h; N2HET2: offset = FFF7 B978h
Figure 23-82. Parity Address Register (HETPAR)
31 16
Reserved
R-0
15 13 12 2 1 0
Reserved PAOFF Reserved
R-0 R-X R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; X = Value unchanged after reset
Table 23-43. Parity Address Register (HETPAR) Field Descriptions
Bit Field Value Description
31-13 Reserved 0 Reads return 0. Writes have no effect.
12-2 PAOFF Parity Error Address Offset. This register holds the offset address of the first parity error, which is
detected in N2HET RAM. This error address is frozen from being updated until it is read by the CPU.
During emulation mode, this address is frozen even when read.
In case of a N2HET RAM parity error, PAOFF will contain the offset address of the erroneous 32-bit
N2HET RAM field counted from the beginning of the N2HET RAM.
Examples: The 32-bit program field of instruction 0 will return 0, the 32-bit control field of instruction 0
will return 1, ..., the 32-bit control field of instruction 1 will return 5, and so on.
Read: Returns the offset address of the erroneous 32-bit word in bytes from the beginning of the
N2HET RAM.
Write: Writes have no effect.
1-0 Reserved 0 Reads return 0. Writes have no effect.
NOTE: The Parity Error Address Register will not be reset, neither by PORRST nor by any other
reset source.