Module Operation
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SPNU563A–March 2018
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Direct Memory Access Controller (DMA) Module
20.2.7 DMA Request
There are three ways to start a DMA transfer:
• Software request: The transfer will be triggered by writing to SW Channel Enable Set and Status
Register (Section 20.3.1.7). The software request can trigger either a block or a frame transfer
depending on the setting of the TTYPE bit in the Channel Control Register (Section 20.3.2.4).
• Hardware request: The DMA controller can handle up to 48 DMA Request lines. A hardware request
can trigger either a frame or a block transfer depending on the setting of the TTYPE bit in the Channel
Control Register (Section 20.3.2.4).
• Triggered by other control packet: When a control packet finishes the programmed number of
transfers it can trigger another channel to initiate its transfers.
Each time a DMA request is made, either one frame transfer or one block transfer can be chosen. An
active DMA request signal will trigger a DMA transaction.
The DMA controller has a two-level buffer to capture HW requests per channel. When a HW request is
generated and the channel is enabled, the corresponding bit in the DMA Status Register
(Section 20.3.1.3) is set. The pending register acts as a first-level buffer. Typically, a peripheral acting as a
source of a transfer could initiate another request after its data registers have been read out by DMA,
even though that data has not been completely transferred to the destination. If a second HW request is
generated by the peripheral, the DMA controller has an extra request buffer to capture this second request
and service it after the first request is complete.
NOTE: The DMA cannot capture more than two requests at the same time. Additional requests are
ignored until at least one pending request is completely processed.
The DMA controller also supports a mix of hardware and software requests on the same channel. Note
that such interchangeable usage may result into an out of sync for DMA channel and peripheral. The
application needs to be careful as the DMA does not have a built-in mechanism to protect against this loss
of synchronization.
If a software request is generated, the corresponding bit in the Channel Pending Register
(Section 20.3.1.2) is set accordingly. If the pending request is not completely serviced by the DMA and a
hardware request is generated by a peripheral onto the same channel, the DMA will capture and
recognize this hardware request into its request buffer.
NOTE: The DMA controller cannot recognize two software requests on the same channel if the first
software request is still pending. If such a request occurs, the DMA will discard it. Therefore,
the user software should check the pending register before issuing a new software request.
The DMA module on this microcontroller has 32 channels and up to 48 hardware DMA requests. The
module contains DREQASIx registers which are used to map the DMA requests to the DMA channels. By
default, channel 0 is mapped to request 0, channel 1 to request 1, and so on.
Some DMA requests have multiple sources, see Table 20-3. The application must ensure that only one of
these DMA request sources is enabled at any time.
(1)
SPI1, SPI2, SPI3, SPI4, SPI5 receive in compatibility mode
(2)
SPI1, SPI2, SPI3, SPI4, SPI5 transmit in compatibility mode
Table 20-3. DMA Request Line Connection
Modules DMA Request Sources DMA Request
MIBSPI1 MIBSPI1[1]
(1)
DMAREQ[0]
MIBSPI1 MIBSPI1[0]
(2)
DMAREQ[1]
MIBSPI2 MIBSPI2[1]
(1)
DMAREQ[2]
MIBSPI2 MIBSPI2[0]
(2)
DMAREQ[3]
MIBSPI1 / MIBSPI3 / DCAN2 MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3 DMAREQ[4]
MIBSPI1 / MIBSPI3 / DCAN2 MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2 DMAREQ[5]
DCAN1 / MIBSPI5 DCAN1 IF2 / MIBSPI5[2] DMAREQ[6]
MIBADC1 / MIBSPI5 MIBADC1 event / MIBSPI5[3] DMAREQ[7]
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