HTU Control Registers
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SPNU563A–March 2018
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High-End Timer Transfer Unit (HTU) Module
24.4 HTU Control Registers
Table 24-10 provides a summary of the registers. The registers support 8-bit, 16-bit, and 32-bit writes. The
offset is relative to the associated peripheral select. See the following sections for detailed descriptions of
the registers. The base address for the control registers is FFF7 A400h for HTU1 and FFF7 A500h for
HTU2. The address locations not listed, are reserved.
Table 24-10. HTU Control Registers
Offset Acronym Register Description Section
00h HTU GC Global Control Register Section 24.4.1
04h HTU CPENA Control Packet Enable Register Section 24.4.2
08h HTU BUSY0 Control Packet Busy Register 0 Section 24.4.3
0Ch HTU BUSY1 Control Packet Busy Register 1 Section 24.4.4
10h HTU BUSY2 Control Packet Busy Register 2 Section 24.4.5
14h HTU BUSY3 Control Packet Busy Register 3 Section 24.4.6
18h HTU ACPE Active Control Packet and Error Register Section 24.4.7
20h HTU RLBECTRL Request Lost and Bus Error Control Register Section 24.4.8
24h HTU BFINTS Buffer Full Interrupt Enable Set Register Section 24.4.9
28h HTU BFINTC Buffer Full Interrupt Enable Clear Register Section 24.4.10
2Ch HTU INTMAP Interrupt Mapping Register Section 24.4.11
34h HTU INTOFF0 Interrupt Offset Register 0 Section 24.4.12
38h HTU INTOFF1 Interrupt Offset Register 1 Section 24.4.13
3Ch HTU BIM Buffer Initialization Mode Register Section 24.4.14
40h HTU RLOSTFL Request Lost Flag Register Section 24.4.15
44h HTU BFINTFL Buffer Full Interrupt Flag Register Section 24.4.16
48h HTU BERINTFL BER Interrupt Flag Register Section 24.4.17
4Ch HTU MP1S Memory Protection 1 Start Address Register Section 24.4.18
50h HTU MP1E Memory Protection 1 End Address Register Section 24.4.19
54h HTU DCTRL Debug Control Register Section 24.4.20
58h HTU WPR Watch Point Register Section 24.4.21
5Ch HTU WMR Watch Mask Register Section 24.4.22
60h HTU ID Module Identification Register Section 24.4.23
64h HTU PCR Parity Control Register Section 24.4.24
68h HTU PAR Parity Address Register Section 24.4.25
70h HTU MPCS Memory Protection Control and Status Register Section 24.4.26
74h HTU MP0S Memory Protection 0 Start Address Register Section 24.4.27
78h HTU MP0E Memory Protection 0 End Address Register Section 24.4.28
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