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STC Control Registers
455
SPNU563A–March 2018
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Self-Test Controller (STC) Module
10.8.10 Signature Compare Self-Check Register (STCSCSCR)
This register is described in Figure 10-23. This register is used to enable the self-check feature of the
CPU Self-Test Controller's (STC) signature compare logic. Self-check can only be done for the STC
interval 0 by setting the RS_CNT bit in STCGCR0 to 1 to restart the self-test. The STC run will fail for
signature miss-compare, provided the signature compare logic is operating correctly. To proceed with
regular CPU self-test, STCSCSCR should be programmed to disable the self-check feature and clear the
RS_CNT bit in STCGCR0 to 0. This register gets reset to its default value with any system reset assertion.
Figure 10-23. Signature Compare Self-Check Register (STCSCSCR) [offset = 3Ch]
31 16
Reserved
R-0
15 5 4 3 0
Reserved FAULT_INS SELF_CHECK_KEY
R-0 R/WP-0 R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after nPORST (power on reset) or System reset
Table 10-18. Signature Compare Self-Check Regsiter (STCSCSCR) Field Descriptions
Bit Field Value Description
31-5 Reserved 0 Reads return 0. Writes have no effect.
4 FAULT_INS Enable fault insertion.
0 No fault is inserted.
1 Insert stuck-at-fault inside CPU so that STC signature compare will fail.
3-0 SELF_CHECK_KEY Signature compare logic self-check enable key.
Ah Signature compare logic self-check is enabled. This allows a fault to be inserted using
the FAULT_INS field.
All other values Signature compare logic self-check is disabled The FAULT_INS field has no effect in
this case.
10.8.11 STC Current ROM Address Register - CORE2 (STCCADDR2)
This register is described in Figure 10-24 and Table 10-19.
NOTE: When the RS_CNT bit in STCGCR0 is set to a 1 on the start of a self-test run, or on a
power-on reset or system reset, this register resets to all zeroes.
Figure 10-24. STC Current ROM Address Register (STCCADDR2) [offset = 40h]
31 0
ADDR
R-0
LEGEND: R = Read only; -n = value after nPORST (power on reset) or System reset
Table 10-19. STC Current ROM Address Register (STCCADDR2) Field Descriptions
Bit Field Description
31-0 ADDR Current ROM Address
This register reflects the current ROM address (address or micro code load) accessed during self-test
Segment0 -Core2. This is the current value of the STC program counter.
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