PBIST Configuration Example
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SPNU563A–March 2018
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Programmable Built-In Self-Test (PBIST) Module
9.6 PBIST Configuration Example
The following examples assume that the PLL is locked and selected as clock source with
GCLK1 = 300 MHz and VCLK = 75 MHz.
9.6.1 Example 1 : Configuration of PBIST Controller to Run Self-Test on DCAN1 RAM
This example explains the configurations for running March13 algorithm on DCAN1.
1. Program the GCLK1 to PBIST ROM clock ratio to 1:4 in System Module.
MSTGCR[9:8] = 2
2. Enable PBIST Controller in System Module.
MSIENA[31:0] = 0x00000001
3. Enable the PBIST self-test in System Module.
MSTGCR[3:0] = 0xA
4. Wait for at least 64 VCLK cycles in a software loop.
5. Enable the PBIST internal clocks.
PACT = 0x1
6. Disable RAM Override. This will make the PBIST controller use the information provided by the
application in the RINFOx and ALGO registers for the memory self-test.
OVER = 0x0
7. Select the Algorithm (refer to Table 2-6).
ALGO = 0x00000004 (Algo 3 = March13N for two-port DCAN1 RAM)
8. Program the RAM group Info to select DCAN1 (DCAN1 RAM is Group 3, refer to Table 2-5).
RINFOL = 0x00000004 (select RAM Group 3)
RINFOU = 0x00000000 (since we are testing only DCAN1)
9. Select both Algorithm and RAM information from on-chip PBIST ROM.
ROM = 0x3
10. Configure PBIST to run in ROM Mode and start PBIST run.
DLR = 0x14
11. Wait for PBIST test to complete by polling MSTDONE bit in System Module.
while (MSTDONE !=1)
12. Once self-test is completed, check the Fail Status register FSRF0.
In case there is a failure (FSRF0 = 1):
a. Read RAMT register that indicates the RGS and RDS values of the failure RAM.
b. Read FSRC0 and FSRC1 registers that contain the failure count.
c. Read FSRA0 and FSRA1 registers that contain the address of first failure.
d. Read FSRDL0 and FSRDL1 registers that contain the failure data.
e. Resume the Test if required using Program Control register (offset = 0x16C) STR = 2.
In case there is no failure (FSRF0 = 0), the memory self-test is completed.
a. Disable the PBIST internal clocks.
PACT = 0
b. Disable the PBIST self-test.
MSTGCR[3:0] = 0x5
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