Introduction
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SPNU563A–March 2018
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Architecture
Table 2-1. Definition of Terms (continued)
Acronym/Term Full Form Description
POM Parameter Overlay Module The parameter overlay module redirects accesses to a programmable region in
flash memory (read-only) to a RAM memory, either on-chip or via the external
memory interface (EMIF). This allows a user to evaluate the impact of changing
values of constants stored in the flash memory without actually having to erase
and reprogram the flash. The POM is also a bus master in this device.
PS_SCR_M Peripheral SCR Master Port All transactions to access the resources in the CPU Interconnect Subsystem by
HTUx, FTU, EMAC, DMM and DAP will funnel through the PS_SCR_S slave
port on the Peripheral Interconnect Subsystem. The PS_SCR_S slave is then
connected to the PS_SCR_M master port on the CPU Interconnect Subsystem
via a NMPU in between.
RTI Real Time Interrupt module RTI module provides timer functionality for operating systems and for
benchmarking code. The module incorporates several counters, which define the
timebases needed for scheduling in the operating system.
SCIx Serial Communication
Interface
The SCI module supports the standard UART in full-duplex mode using the
standard Non-Return-to-Zero (NRZ) format.
SCM SCR Control Module This module is used to change certain configurations such as timeout counters
of the CPU Interconnect Subsystem. This module is also used to initiate selftest
for the CPU Interconnect Subsystem.
SDC MMR Safety Diagnostic Checker
Memory-Map Register Port
for CPU Interconnect
Subsystem
There are memory-mapped status registers to record both the run-time and self-
test diagnostic of the CPU Interconnect Subsystem. These registers are
accessed via the SDC MMR slave port in the Peripheral Interconnect
Subsystem.
SRAM Level 2 Static RAM There is one slave port to access the on-chip SRAM.
STCx Selftest Controller There are two STC modules in this device. One is used to test the CPU
subsystem including both CPU cores and/or the ACP component using the
Deterministic Logic Bist Controller as the test engine. The other STC is used to
test either or both the N2HETs in the device.
SYS System Module This module contains the housekeeping logic to control and log overall system
functions and status such as setting up the clock sources, clock domains,
generation and reception of reset sources.
µSCU Micro Snooping Control Unit The µSCU which is part of the Cortex-R5 processor system contains an ACP
(Accelerator Coherency Port) interface which provides snoop capabilities on
write-transactions coming from the non-CPU masters. Transactions are received
on the ACP-S slave port, and transmitted on the memory system via the ACP-M
master port. The ACP automatically invalidates the appropriate Level 1 data-
cache lines at the appropriate time, allowing software maintenance free cache
coherency for data in write-through cache regions, as well as non-cached.
VIM Vectored Interrupt Manager VIM provides hardware assistance for prioritizing and controlling the many
interrupt sources present on a device. There are two VIMs in this device. When
the device is configured in lockstep mode, the two VIMs are also in lockstep.
The outputs of the two VIMs are compared cycle by cycle by the CCM-R5
module.
2.1.3 Bus Master / Slave Access Privileges
This device implements some restrictions on the bus slave access privileges in order to improve the
overall throughput of the interconnect shown in Figure 2-1. Table 4-1 shows the implemented point to
point connections between the masters and slaves connected to the Peripheral Interconnect Subsystem.
Table 4-3 lists the implemented point to point connections between the masters and slaves connected to
the CPU Interconnect Subsystem.
2.1.4 CPU Interconnect Subsystem SDC MMR Port
The CPU Interconnect Subsystem SDC MMR Port is a special slave to the Peripheral Interconnect
Subsystem. It is memory-mapped at starting address of FA00 0000h. Various status registers pertaining to
the diagnostics of the CPU Interconnect Subsystem can be access through this slave port. The CPU
Interconnect Subsystem contains built-in hardware diagnostic checkers which will constantly watch
transactions flowing through the interconnect. There is a checker for each master and slave attached to
the CPU Interconnect Subsystem. The checker checks the expected behavior against the generated