HTU Control Registers
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SPNU563A–March 2018
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High-End Timer Transfer Unit (HTU) Module
24.4.12 Interrupt Offset Register 0 (HTU INTOFF0)
The INTOFF0 register reflects the highest priority interrupt flag bit set in the BERINTFL, RLOSTFL, or
BFINTFL flag registers with the appropriate CPINTMAP bit set to 0. The priority order (from high to low) is:
BER, RLOST, buffer-full. Interrupts for request lines with lower number have higher priority.
Figure 24-25. Interrupt Offset Register 0 (HTU INTOFF0) [offset = 34h]
31 16
Reserved
R-0
15 10 9 8 7 4 3 0
Reserved INTTYPE0 Reserved CPOFF0
R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 24-24. Interrupt Offset Register 0 (HTU INTOFF0) Field Descriptions
Bit Field Value Description
31-10 Reserved 0 Reads return 0. Writes have no effect.
9-8 INTTYPE0 Interrupt Type of Interrupt Line 0. Indicates whether a buffer-full, RLOST, or BER interrupt, assigned to
interrupt line 0, is currently pending.
0 No interrupt.
1h Interrupt caused by full buffer on CP/DCP specified by CPOFF0.
2h RLOST interrupt generated by CP/DCP specified by CPOFF0.
3h BER interrupt generated by CP/DCP specified by bits CPOFF0.
7-4 Reserved 0 Reads return 0. Writes have no effect.
3-0 CPOFF0 CP Offset. Indicates for which control packet the interrupt is pending, which is classified by INTTYPE0
and is assigned to interrupt line 0.
0 DCP 0, CP A
1h DCP 0, CP B
2h DCP 1, CP A
3h DCP 1, CP B
4h DCP 2, CP A
5h DCP 2, CP B
6h DCP 3, CP A
7h DCP 3, CP B
8h DCP 4, CP A
9h DCP 4, CP B
Ah DCP 5, CP A
Bh DCP 5, CP B
Ch DCP 6, CP A
Dh DCP 6, CP B
Eh DCP 7, CP A
Fh DCP 7, CP B
NOTE: Reading CPOFF0 will clear the bit generating the current interrupt from appropriate flag
register (BERINTFL, RLOSTFL, or BFINTFL), except when in debug mode where reading
CPOFF0 will have no effect on the flag registers.
In order to read INTTYPE0 and CPOFF0 simultaneously, always read this register using
word or half-word but not using byte accesses.
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