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Control Registers
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SPNU563A–March 2018
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Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
28.3.8 SPI Pin Control Register 2 (SPIPC2)
NOTE: Register bits vary by device
Register bits 31:24 and 23:16 of this register reflect the number of SIMO/SOMI data lines per
device. On devices with 8 data-line support, all of bits 31 to 16 are implemented. On devices
with less than 8 data lines, only a subset of these bits are available. Unimplemented bits
return 0 upon read and are not writable.
Figure 28-39. SPI Pin Control Register 2 (SPIPC2) [offset = 1Ch]
31 24 23 16
SOMIDIN SIMODIN
R/W-U R/W-U
15 12 11 10 9 8
Reserved SOMIDIN0 SIMODIN0 CLKDIN ENADIN
R-0 R-U R-U R-U R-U
7 0
SCSDIN
R/W-U
LEGEND: R/W = Read/Write; R = Read only; U = value is undefined; -n = value after reset
Table 28-16. SPI Pin Control Register 2 (SPIPC2) Field Descriptions
Bit Field Value Description
31-24 SOMIDIN SPISOMIx data in. The value of the SPISOMIx pins.
0 SPISOMIx pin is logic 0.
1 SPISOMIx pin is logic 1.
23-16 SIMODIN SPISIMOx data in. The value of the SPISIMOx pins.
0 SPISIMOx pin is logic 0.
1 SPISIMOx pin is logic 1.
15-12 Reserved 0 Reads return 0. Writes have no effect.
11 SOMIDIN0 SPISOMI0 data in. The value of the SPISOMI0 pin.
0 SPISOMI0 pin is logic 0.
1 SPISOMI0 pin is logic 1.
10 SIMODIN0 SPISIMO0 data in. The value of the SPISIMO0 pin.
0 SPISIMO0 pin is logic 0.
1 SPISIMO0 pin is logic 1.
9 CLKDIN Clock data in. The value of the SPICLK pin.
0 SPICLK pin is logic 0.
1 SPICLK pin is logic 1.
8 ENADIN SPIENA data in. The value of the SPIENA pin.
0 SPIENA pin is logic 0.
1 SPIENA pin is logic 1.
7-0 SCSDIN SPICS data in. The value of each SPICS pin.
0 SPICS pin is logic 0.
1 SPICS pin is logic 1.
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