www.ti.com
HWAG Registers
1053
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
High-End Timer (N2HET) Module
23.5.11 HWAG Interrupt Offset Register 1 (HWAOFF1)
This register is a read-only register and provides a numerical value that represents the pending interrupt
with a low priority. The index can be used to locate the interrupt routine position in the vector table. A read
to this register clears the corresponding interrupt pending bit in the HWAG interrupt flag register
(HWAFLG). An interrupt pending bit in the HWAFLG register is the bit for which the corresponding
interrupt enable bit is set.
During suspend mode, a read to this register does not clear the corresponding interrupt bit.
Figure 23-99. HWAG Interrupt Offset Register 1 (HWAOFF1)
31 16
Reserved
R-0
15 8 7 0
Reserved OFFSET2
R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 23-63. HWAG Interrupt Offset Register 1 (HWAOFF1) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reads return 0. Writes have no effect.
7-0 OFFSET2
Low-Priority Interrupt Offset.. These bits give the offset for the corresponding interrupts.
0 Phantom interrupt
1 Overflow period
2 Singularity not found
3 Tooth interrupt
4 ACNT overflow
5 PCNT(n) > 2 × PCNT (n-1) during normal tooth
6 Bad active edge tooth
7 Gap flag
8 Angle increment overflow
To Next Page
Loading...
Need help?
General
