reference
Input
Feedback
divider output
Down
Up
Lagging phase
Leading phase
VCO control
voltage
Interpulse slope caused by filter time constant and leakage
PFD CP LF
VCO
÷NF
CLKIN
÷2
÷2
÷NR
÷R
PLL CLK
÷OD
post-ODCLK
INTCLK
Output CLK
Feedback
CLK
Phase-Locked Loop Theory of Operation
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SPNU563A–March 2018
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Oscillator and PLL
14.7 Phase-Locked Loop Theory of Operation
The PLL block consists of six logical sub-blocks:
• Phase-Frequency Detector (PFD)
• Charge Pump (CP)
• Loop Filter (LF)
• Voltage-Controlled Oscillator (VCO)
• Frequency Modulation
• Slip Detector
Figure 14-9 illustrates the sub-blocks in a basic PLL circuit. The VCO adjusts its frequency until the two
signals into the PFD have the same phase and frequency. The feedback path (from VCO to PFD) divides
the frequency of the feedback signal by 2 × NF; this feedback divider requires the VCO to generate a
frequency 2 × NF times greater than the internal frequency (OSCIN/NR). In the forward path (from VCO to
PLL CLK), the /2 block creates a clean duty cycle.
Figure 14-9. Basic PLL Circuit
14.7.1 Phase-Frequency Detector
The phase-frequency detector (PFD) compares the input reference phase/frequency to the
phase/frequency of the feedback divider and generates two signals: an up pulse and a down pulse that
drive a charge pump. The resulting charge, when integrated by the circuit at the LF pin, provides a VCO
control voltage, as shown in Figure 14-10.
Figure 14-10. PFD Timing
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