Flash Control Registers
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SPNU563A–March 2018
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F021 Level 2 Flash Module Controller (L2FMC)
7.10.25 Parity Override Register (FPAR_OVR)
This register allows overriding the parity that is internally computed by the L2FMC for checking the parity
circuit.
Figure 7-35. Parity Override Register (FPAR_OVR) (offset = 7Ch)
31 18 17 16
Reserved PAR_OVR_SEL
R-0 R/WP-0
15 12 11 9 8 0
PAR_DIS_KEY PAR_OVR_KEY Reserved
R/WP-5h R/WP-2h R-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in Privilege Mode; -n = value after reset
Table 7-37. Parity Override Register (FPAR_OVR) Field Descriptions
Bit Field Value Description
31-18 Reserved 0 Reserved
17-16 PAR_OVR_SEL Select which parity checker to invert the polarity of the parity.
0 No effect.
1h Idle state parity checker received inverted parity polarity.
2h Command parity checker receives inverted parity polarity.
3h Internal address parity checker receives inverted parity polarity
15-12 PAR_DIS_KEY Disable access Parity. ECC on Data is NOT affected by this setting and behaves the same
way.
Ah The access parity error is disabled and no checking is done and no events are generated.
All other values Any other value enables the parity checking on the access.
11-9 PAR_OVR_KEY Parity Override
5h The selected parity checker selected through PAR_OVR_SEL will receive inverted
SYS_ODD_PARITY.
All other values Any other value causes the module to use the global system parity bit in the system register
DEVCR1.
8-0 Reserved 0 Reads return 0. Writes have no effect.
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