DCAN Control Registers
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SPNU563A–March 2018
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Controller Area Network (DCAN) Module
27.17.9 ECC Diagnostic Register (DCAN ECCDIAG)
Figure 27-28. ECC Diagnostic Register (DCAN ECCDIAG) [offset = 24h]
31 16
Reserved
R-0
15 4 3 0
Reserved ECCDIAG
R-0 R/WP-Ah
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset; U = Undefined
Table 27-15. ECC Diagnostic Register (DCAN ECCDIAG) Field Descriptions
Bit Field Value Description
31-4 Reserved 0 These bits are always read as 0. Writes have no effect.
3-0 ECCDIAG SECDED diagnostic mode enable.
5h Diagnostic mode is enabled. Single-bit and double-bit errors are shown in the ECCDIAG
STAT and the ECC Control and Status register. A double-bit error (or single-bit error with
single-bit error correction disabled) also triggers the parity interrupt flag (PER). Memory
mapping of ECC RAM is enabled.
Ah Diagnostic mode is disabled, single-bit and double-bit errors are shown only in the ECC
Control and Status register.
All other values Reserved
27.17.10 ECC Diagnostic Status Register (DCAN ECCDIAG STAT)
Figure 27-29. ECC Diagnostic Status Register (DCAN ECCDIAG STAT) [offset = 28h]
31 16
Reserved
R-0
15 9 8 7 1 0
Reserved DEFLG_DIAG Reserved SEFLG_DIAG
R-0 R/W1C-0 R-0 R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear; -n = value after reset; U = Undefined
Table 27-16. ECC Diagnostic Status Register (DCAN ECCDIAG STAT) Field Descriptions
Bit Field Value Description
31-9 Reserved 0 These bits are always read as 0. Writes have no effect.
8 DEFLG_DIAG Double-bit error flag diagnostic.
0
Read: No double-bit error is detected.
Write: The bit is unchanged.
1
Read: Double-bit error is detected in diagnostic mode.
Write: The bit is cleared to 0.
7-1 Reserved 0 These bits are always read as 0. Writes have no effect.
0 SEFLG_DIAG Single-bit error flag diagnostic.
0
Read: No single-bit error is detected.
Write: The bit is unchanged.
1
Read: Single-bit error is detected in diagnostic mode.
Write: The bit is cleared to 0.
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