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Basic Operation
853
SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
Analog To Digital Converter (ADC) Module
22.1.1.4 Sequencer
The sequencer coordinates the operations of the ADC, including the input multiplexor, the ADC core, and
the result memory. In addition, the logic of the sequencer sets the status register flags when the
conversion is ongoing, stopped, or finished.
All the features of the sequencer are discussed in detail in the following sections of this document.
22.1.1.5 Conversion Groups
Several applications require groups of channels to be converted using a single trigger source for example.
There could also be some groups of channels identified which require a specific setting of the acquisition
time. The ADC module supports three conversion groups for this purpose – Group1, Group2 and the
Event Group.
Any of the available analog input channels can be assigned to any of the conversion groups. This also
allows a particular channel to be repeatedly sampled by selecting it in multiple groups. There is an
inherent priority scheme used when multiple conversion groups are triggered at once. The Event Group is
the highest-priority, followed by the Group1 and then the Group2.
The Event Group is always hardware event-triggered. Group1 and Group2 are software-triggered by
default and can be configured to be hardware-, or event-triggered as well. The triggering of conversions in
each group is discussed in Section 22.2.1.6.
Each conversion group has a separate set of control registers to:
• Select the input channels to be converted
• Configure the mode of conversion: single conversion sequence or continuous conversions
• Configure the input channel sampling time
• Configure the interrupt and/or DMA request generation conditions
22.2 Basic Operation
22.2.1 Basic Features and Usage of the ADC
This section describes the usage of the basic features of the ADC module.
22.2.1.1 How to Select Between 12-bit and 10-bit Resolutions
The 10_12_BIT field of the ADC Operating Mode Control Register (ADOPMODECR) configures the ADC
to be in 10-bit or 12-bit resolution mode:
• If 10_12_BIT = 0, the module is in 10-bit resolution mode. This is the default mode of operation.
• If 10_12_BIT = 1, the module is in 12-bit resolution mode.
22.2.1.2 How to Set Up the ADCLK Speed
The ADC sequencer generates the clock for the ADC core, ADCLK. The ADC core uses the ADCLK
signal for its timing. The ADCLK is generated by dividing down the input clock to the ADC module, which
is the VBUSP interface clock, VCLK. A 5-bit field (PS) in the ADC Clock Control Register (ADCLOCKCR)
is used to divide down the VCLK by 1 up to 32. The ADCLK valid frequency range is specified in the
device datasheet.
f
ADCLK
= f
VCLK
/ (PS + 1)
The maximum frequency for ADCLK is specified in the device datasheet.
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