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Module Operation
701
SPNU563A–March 2018
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Direct Memory Access Controller (DMA) Module
20.2.3 Addressing Modes
There are three addressing modes supported by the DMA controller that can be setup independent for the
source and the destination address:
• Constant -- source and/or destination addresses do not change.
• Post incremented -- source and/or destination address are post-incremented by the element size.
• Indexed -- source and/or destination address is post-incremented as defined in the Element Index
Offset Register (Section 20.3.2.5) and the Frame Index Offset Register (Section 20.3.2.6).
An unaligned address with respect to the element size is not supported.
20.2.4 DMA Channel Control Packets
Corresponding to each logical channel is a control packet that is mapped in fixed numerical order. For
example, control packet 0 stores channel information for channel 0. The DMA requests can be mapped to
the individual channels as described in Section 20.2.7. The mapping scheme between DMA requests and
channels is shown in Figure 20-4. Each control packet contains nine fields. The first six fields compose the
primary control packet and are programmable during DMA setup. The last three fields compose working
control packet and are only readable by the CPU. The working control packets are used to support auto-
initiation and prioritization of channels.. The organization of control packets is shown in Figure 20-5.
The primary control packet contains channel information such as source address, destination address,
transfer count, element/frame offset value and channel configuration. Source address, destination address
and transfer count also have their respective working images. The three fields of working images compose
a working control packet and are not accessible to the CPU in write access.
The first time a DMA channel is selected for a transaction, the following process occurs:
1. The primary control packet is first read by the DMA state machine.
2. Once the channel is arbitrated, the current source address, destination address and transfer count are
then copied to their respective working images.
3. When the channel is serviced again by the DMA, the state machine will read both the primary control
packet and the working control packet to continue the DMA transaction until the end of an entire block
transfer.
When the same channel is requested again, the state machine will start again by reading only the primary
control packet and then continue the same process described above. The user software need not set up
control packets again because the contents of the primary control packet were never lost. The working
images of the control packets are reducing the software overhead and interaction with the DMA module to
a minimum.
NOTE: Changing the contents of a channel control packet will clear the corresponding pending bit
(Section 20.3.1.2) if the channel has a pending status. If the control packet of an active
channel (as indicated in Section 20.3.1.3) is changed, then the channel will stop immediately
at an arbitration boundary. When the same channel is triggered again, it will begin with the
new control packet information.
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