Overview
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SPNU563A–March 2018
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Level 2 RAM (L2RAMW) Module
8.1 Overview
The Level 2 RAM (L2RAM) module controls and decodes RAM memory accesses on this device.
Features of the L2RAM are:
• Controls read/write accesses to the data RAM
• Decodes addresses within the memory region allocated for the RAM
• Performs ECC check on all incoming CPU writes to ensure that data is intact
• Supports read and write accesses in 64-bit, 32-bit, 16-bit, or 8-bit access sizes
– Performs redundant ECC check on merged data during read-modify-write operations
– Does not support bit-wise operations
• Safety Features:
– Single-Error-Correction Double-Error-Detection (SECDED) on data
• Uses the CPU's Event bus and maintains the SECDED status in memory-mapped registers
• Captures the number of occurrences of single-bit or multi-bit errors as well as the RAM address
that has the fault
• Generates error signals for single-bit and multi-bit errors to the Error Signaling Module (ESM)
– Performs Memory Scrubbing to Identify and Correct Single Bit RAM errors in the L2RAM memory
– SECDED Malfunction Checking to Verify that L2RAMW ECC is functioning correctly
– Parity Protection of the Address Bus and Control Signals
• Generates error signals for parity error to the Error Signaling Module (ESM)
– Redundant Address Decode Scheme
• Checks the decoding of CPU address lines and generation of correct memory selects for the
RAM banks
• Exclusive access support
• Supports auto-initialization of the CPU data RAM banks
• Supports the RAM Trace Port (RTP) Interface
– Traces out all RAM read and write accesses to the RTP module
8.2 Module Operation
8.2.1 RAM Memory Map
The L2RAMW decodes 8MB of data space. Up to 512kB of implemented data space is supported. Check
the specific part's datasheet to identify the actual amount of RAM supported on the device. This RAM is
protected by ECC, allowing the CPU to correct any single-bit errors and detect multi-bit errors within a 64-
bit value. The error correction code (ECC) values are stored in the RAM memory space as well. The
memory map for the RAM and the corresponding ECC space is shown in Figure 8-1. Any access to an
unimplemented RAM location results in an error response from the L2RAMW module.
Each RAM data word is 64-bits wide. These 64 bits are divided into 32 bits per RAM bank. The 8 bits of
ECC are also divided into 4 bits per RAM bank.
For every 64-bit read from the RAM, an 8-bit ECC is also read by the CPU on its ECC bus. Similarly, for
every 64-bit write to the RAM, the CPU also writes an 8-bit ECC using the same ECC bus.
The ECC memory can also be directly accessed via memory-mapped offset addresses. A read from the
ECC space results in the 8-bit ECC value appearing on each byte of the 64-bit CPU data. Writes to ECC
memory must be 64-bit aligned. Writes to the ECC space must also first be enabled via the RAM Control
Register (RAMCTRL).
Accesses to the ECC space are not traced out to the RAM Trace Port (RTP).
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