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Module Operation
1215
SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
FlexRay Module
Table 26-1. FlexRay Address Range Table
Module Address Range
FlexRay Communication Controller 0xFFF7_C800 - 0xFFF7_CFFF
FlexRay TU 0xFFF7_A000 - 0xFFF7_A1FF
FlexRay TU RAM 0xFF50_0000 - 0xFF51_FFFF
26.2 Module Operation
26.2.1 Transfer Unit
The FlexRay Transfer Unit (FTU), Figure 26-3, has an internal intelligent state-machine (Transfer Unit
State Machine) to transfer data between the Input and Output Buffer Interfaces of the FlexRay core
module and the system memory of the microcontroller without CPU interaction. It operates in a similar
manner to a DMA (Direct Memory Access) module.
The FlexRay Input Buffer (IBF) and FlexRay Output Buffer (OBF) can also be accessed directly by the
CPU. In this case the IBF and OBF are 8-, 16-, and 32-bit accessible. For transfers using the Transfer Unit
State Machine only 4 × 32-bit data packages (4 word bursts) are supported.
The Interface Arbiter controls the access to the IBF and OBF. Direct CPU accesses to IBF and OBF are
not possible, if the Transfer Unit State Machine is switched on. Accesses will be ignored and the
associated error interrupt will be generated.
The Transfer Unit State Machine is the head of all manual, event driven and automatic message transfer
activities. It controls the Transfer Unit interrupt generation related to transfer protocol correctness, status
and violations of the message transfers.
With the Transfer Configuration RAM (TCR) the transfer sequence, executed by the Transfer Unit State
Machine, can be configured.
The usage of the Transfer Unit allows the user to setup a mirror of the FlexRay message RAM in the fast
accessible data RAM of the microcontroller. The Transfer Unit can handle the data transfers between the
data RAM and the FlexRay message RAM in the ‘background’ without CPU interaction.
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