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GIO Control Registers
1207
SPNU563A–March 2018
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General-Purpose Input/Output (GIO) Module
25.5.15 GIO Data Clear Registers (GIODCLR[A-B])
Values in this register clear the data output register (GIO Data Output Register [A-H]) bit to 0 regardless of
its current value. The contents of this register reflect the contents of GIODOUT. Figure 25-21 and
Table 25-18 describe this register.
Figure 25-21. GIO Data Clear Registers (GIODCLR[A-B]) [offset = 44h, 64h]
31 16
Reserved
R-0
15 8 7 0
Reserved GIODCLR[7:0]
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-18. GIO Data Clear Registers (GIODCLR[A-B]) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reads return 0. Writes have no effect.
7-0 GIODCLR[n] GIO data clear for port n, pins[7:0]. This bit drives the output of GIO pin low.
0 Write: Writing a 0 has no effect.
1 Write: The corresponding GIO pin is driven to logic low (0).
Note: The current logic state of the GIODOUT bit will also be displayed by this bit.
Note: GIO pin is placed in output mode by setting the GIODIRx bit to 1.
25.5.16 GIO Open Drain Registers (GIOPDR[A-B])
Values in this register enable or disable the open drain capability of the data pins. Figure 25-22 and
Table 25-19 describe this register.
Figure 25-22. GIO Open Drain Registers (GIOPDR[A-B]) [offset = 48h, 68h]
31 16
Reserved
R-0
15 8 7 0
Reserved GIOPDR[7:0]
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-19. GIO Open Drain Registers (GIOPDR[A-B]) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reads return 0. Writes have no effect.
7-0 GIOPDR[n] GIO open drain for port n, pins[7:0]
0 The GIO pin is configured in push/pull (normal GIO) mode. The output voltage is V
OL
or lower if
GIODOUT bit = 0 and V
OH
or higher if GIODOUT bit = 1.
1 The GIO pin is configured in open drain mode. The GIODOUTx bit controls the state of the GIO
output buffer: GIODOUTx = 0, the GIO output buffer is driven low; GIODOUTx = 1, the GIO output
buffer is tristated.