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SPNU563A–March 2018
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Direct Memory Access Controller (DMA) Module
20.1.2 System Resources Mapping
Table 20-1 shows how the system resources are mapped to either of the two DMA ports. In order to
properly transfer data from one resource to another, the application must setup the PARx register
according to Table 20-1.
Table 20-1. DMA Ports to System Resources Mapping
DMA Ports System Resources
Port A
• L2 Flash
• L2 SRAM
• EMIF
Port B
• All peripherals, that is, MibSPI registers, DCAN registers
• All peripheral memories, that is, MibSPI RAM, DCAN RAM
• Example 1: To transfer data from L2 Flash, L2 SRAM, or EMIF to any peripheral registers or peripheral
memories, write 0x1 (Port A read, Port B write ) to the respective channels in the PARx registers
• Example 2: To transfer data from any peripheral registers or peripheral memories to L2 SRAM or
EMIF, write 0x0 (Port B read, Port A write ) to the respective channels in the PARx registers
• Example 3: To transfer data from L2 Flash to L2 SRAM, write 0x2 (Port A) to the respective channels
in the PARx registers
• Example 4: To transfer data from peripherals to another peripherals, write 0x3 (Port B) to the
respective channels in the PARx registers.
20.2 Module Operation
The DMA acts as an independent master in the platform architecture. DMA will attempt to execute up to
two channels at the same time to maximize system throughput. Each channel can be configured to utilize
either Port A or B or both for the read and write accesses while storing the data in one of the FIFOs.
Choice of Port A or Port B for a certain channel depends on the addresses chosen for the transfer and
should be made by referring to Table 20-1. All DMA memory and register accesses are performed in user
mode. If the DMA writes to registers which are only accessible in privileged mode, the write will not be
performed.
The DMA registers and its local RAM can only be accessed in privilege mode. Therefore, it is not possible
for the DMA to reprogram itself.
In order to further explain DMA operation, some terms are described below:
• Arbitration - A channel may get temporarily suspended in order to service a higher priority channel or
when the channel is disabled on the fly. The channel is said to have been "arbitrated"
• Arbitration Boundary - Each time a channel finishes a chunk of transfer which can be a maximum of 32
bytes, it is said to have reached an arbitration boundary. The FIFO is empty at an arbitration boundary.
The DMA will utilize this boundary to re-prioritize channels. Within an arbitration boundary, transfers
can never be interrupted.
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