Texas Instruments TMS570LC4357

Event manager (prioritization,
arbitration)
DMA req sync
and polarity
FIFO A channel
processing
FIFO B channel
processing
Port Arbiter
Control Packet
Access Arbiter
Control
Regs
Control
Packet
RAM
Interrupt
Manager
Port A Port B
BTC, FTC, BER,
LFS, HBC, MPV
interrupts
CPU I/F
Errors (Single,
Double Bit Errors)
Hardware Events
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SPNU563A–March 2018
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Direct Memory Access Controller (DMA) Module
Figure 20-1. DMA Block Diagram