Texas Instruments TMS570LC4357

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1033
SPNU563A–March 2018
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High-End Timer (N2HET) Module
23.4.19 N2HET Data Input Register (HETDIN)
N2HET1: offset = FFF7 B850h; N2HET2: offset = FFF7 B950h
Figure 23-74. N2HET Data Input Register (HETDIN)
31 16
HETDIN
R-x
15 0
HETDIN
R-x
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset;
Table 23-35. N2HET Data Input Register (HETDIN) Field Descriptions
Bit Field Value Description
31-0 HETDIN[n] Data input. This bit displays the logic state of the pin.
0 Pin HET[n] is at logic low (0).
1 Pin HET[n] is at logic high (1).
23.4.20 N2HET Data Output Register (HETDOUT)
N2HET1: offset = FFF7 B854h; N2HET2: offset = FFF7 B954h
Figure 23-75. N2HET Data Output Register (HETDOUT)
31 16
HETDOUT
R/W-0
15 0
HETDOUT
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-36. N2HET Data Output Register (HETDOUT) Field Descriptions
Bit Field Value Description
31-0 HETDOUT[n] Data out write. Writes to this bit will only take effect when the pin is configured as an output. The
current logic state of the pin will be displayed by this bit even when the pin state is changed by
writing to HETDSET or HETDCLR.
0 Pin HET[n] is at logic low (0).
1 Pin HET[n] is at logic high (1) if the HETPDR[n] bit = 0 or the output is in high-impedance state if
the HETPDR[n] bit = 1.