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CRC Control Registers
641
SPNU563A–March 2018
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Cyclic Redundancy Check (CRC) Controller Module
18.3.4.1 CRC Setup
• All control registers can be left in their reset state. Only enable Full-CPU mode.
CPU itself reads from the memory and write the data to the PSA Signature Register inside CRC
Controller. When the first incoming data pattern arrives at the PSA Signature Register, the CRC Controller
will compress it. After 2MBytes data patterns are compressed, CPU can read from the PSA Signature
Register. It is up to the CPU on how to deal with the PSA signature value just read. It can compare it to a
known signature value stored at another memory location.
18.4 CRC Control Registers
All registers are in word boundary. 64, 32, 16, and 8 bit write accesses are supported to all registers. The
base address for the control registers is FE00 0000h for CRC1 and FB00 0000h for CRC2.
Table 18-4. CRC Control Registers
Offset Acronym Register Description Section
0h CRC_CTRL0 CRC Global Control Register Section 18.4.1
8h CRC_CTRL1 CRC Global Control Register 1 Section 18.4.2
10h CRC_CTRL2 CRC Global Control Register 2 Section 18.4.3
18h CRC_INTS CRC Interrupt Enable Set Register Section 18.4.4
20h CRC_INTR CRC Interrupt Enable Reset Register Section 18.4.5
28h CRC_STATUS CRC Interrupt Status Register Section 18.4.6
30h CRC_INT_OFFS_ET_REG CRC Interrupt Offset Register Section 18.4.7
38h CRC_BUSY CRC Busy Register Section 18.4.8
40h CRC_PCOUNT_REG1 CRC Channel 1 Pattern Counter Preload Register Section 18.4.9
44h CRC_SCOUNT_REG1 CRC Channel 1 Sector Counter Preload Register Section 18.4.10
48h CRC_CURSEC_REG1 CRC Channel 1 Current Sector Register Section 18.4.11
4Ch CRC_WDTOPLD1 CRC Channel 1 Watchdog Timeout Preload Register Section 18.4.12
50h CRC_BCTOPLD1 CRC Channel 1 Block Complete Timeout Preload Register Section 18.4.13
60h PSA_SIGREGL1 Channel 1 PSA Signature Low Register Section 18.4.14
64h PSA_SIGREGH1 Channel 1 PSA Signature High Register Section 18.4.15
68h CRC_REGL1 Channel 1 CRC Value Low Register Section 18.4.16
6Ch CRC_REGH1 Channel 1 CRC Value High Register Section 18.4.17
70h PSA_SECSIGREGL1 Channel 1 PSA Sector Signature Low Register Section 18.4.18
74h PSA_SECSIGREGH1 Channel 1 PSA Sector Signature High Register Section 18.4.19
78h RAW_DATAREGL1 Channel 1 Raw Data Low Register Section 18.4.20
7Ch RAW_DATAREGH1 Channel 1 Raw Data High Register Section 18.4.21
80h CRC_PCOUNT_REG2 CRC Channel 2 Pattern Counter Preload Register Section 18.4.22
84h CRC_SCOUNT_REG2 CRC Channel 2 Sector Counter Preload Register Section 18.4.23
88h CRC_CURSEC_REG2 CRC Current Sector Register 2 Section 18.4.24
8Ch CRC_WDTOPLD2 CRC Channel 2 Watchdog Timeout Preload Register A Section 18.4.25
90h CRC_BCTOPLD2 CRC Channel 2 Block Complete Timeout Preload Register B Section 18.4.26
A0h PSA_SIGREGL2 Channel 2 PSA Signature Low Register Section 18.4.27
A4h PSA_SIGREGH2 Channel 2 PSA Signature High Register Section 18.4.28
A8h CRC_REGL2 Channel 2 CRC Value Low Register Section 18.4.29
ACh CRC_REGH2 Channel 2 CRC Value High Register Section 18.4.30
B0h PSA_SECSIGREGL2 Channel 2 PSA Sector Signature Low Register Section 18.4.31
B4h PSA_SECSIGREGH2 Channel 2 PSA Sector Signature High Register Section 18.4.32
B8h RAW_DATAREGL2 Channel 2 Raw Data Low Register Section 18.4.33
BCh RAW_DATAREGH2 Channel 2 Raw Data High Register Section 18.4.34
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