Texas Instruments TMS570LC4357

STC1 Segment 1 (µSCU) Test Coverage and Duration www.ti.com
444
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Self-Test Controller (STC) Module
10.6 STC1 Segment 1 (µSCU) Test Coverage and Duration
The test coverage and number of test execution cycles (STCCLK) for each test interval are shown in
Table 10-4.
Table 10-4. STC1 Segment 1 Test Coverage and Duration
Intervals Test Coverage (%) Test Time (Cycles)
0 0 0
1 84.79 1629
2 87.96 3258
3 88.33 4887
Table 10-5 gives the typical STC execution times for 3 intervals at different clock rates. You can choose
the number of intervals to be run based on the coverage needed and allowed time for STC execution.
Table 10-5. Typical Execution Times for STC1 Segment 1
Number of Intervals Coverage
@ GCLK1 = 330 MHz
STCCLK = 110 MHz
@ GCLK1 = 300 MHz
STCCLK = 100 MHz
3 >88% 44.43 µS 48.87 µS
10.7 STC2 (nHET) Test Coverage and Duration
The test coverage and number of test execution cycles (STCCLK) for each test interval are shown in
Table 10-6.
Table 10-6. STC2 Test Coverage and Duration
Intervals Test Coverage (%) Test Time (Cycles)
0 0 0
1 70.01 1365
2 77.89 2730
3 81.73 4095
4 84.11 5460
5 86.05 6825
6 87.78 8190
7 88.96 9555
8 89.95 10920
9 90.63 12285
10 91.20 13650
11 91.60 15015
12 92.02 16380
13 92.37 17745
14 92.66 19110
15 92.87 20475
16 93.04 21840
17 93.26 23205
18 93.47 24570
19 93.67 25935
20 93.82 27300
21 93.96 28665
22 94.12 30030