Block
Element 1
Element 2
Frame 1
Element Count = 2
Element 3
Element 4
Frame 2
Element 5
Element 6
Frame 3
Element 7
Element 8
Frame 4
Frame count = 4
DMAREQ
Trigger Source = block transfer triggered by DMA request
Block
Element 1
Element 2
Frame 1
Element Count = 2
Element 3
Element 4
Frame 2
Element 5
Element 6
Frame 3
Element 7
Element 8
Frame 4
Frame count = 4
DMAREQ DMAREQ DMAREQ DMAREQ
Trigger Source = frame transfer triggered by DMA request
Module Operation
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SPNU563A–March 2018
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Direct Memory Access Controller (DMA) Module
20.2.1 Memory Space
The DMA controller makes no distinction between program memory and data memory. The DMA
controller can transfer to and from any space within the 4 gigabyte physical address map, by programming
the absolute address for the source and destination in the control packet. Control packets store the
transfer information such as source address, destination address, transfer count and control attributes for
each channel.
20.2.2 DMA Data Access
The DMA controller refers to data in three levels of granularity:
• Element: Depending on the programmed data type, an 8-bit, 16-bit, 32-bit, or a 64-bit value. The type
can be individually selected for the source (read) and destination (write). See Figure 20-2 and
Figure 20-3 for an example of the use of elements. An element transfer cannot be interrupted.
• Frame: One or more elements to be transferred as a unit. A frame transfer can be interrupted between
element transfers. See Figure 20-2 for an example. Use a frame size of one and frame transfer trigger
source for transfers of one element per request.
• Block: One or more frames to be transferred as a unit. Each channel can transfer one block of data
(once or multiple times). See Figure 20-3 for an example.
Figure 20-2. Example of a DMA Transfer Using Frame Trigger Source
Figure 20-3. Example of a DMA Transfer Using Block Trigger Source
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