EMIF_nCS[n]
EMIF_nWE
EMIF_nOE
EMIF_WAIT
EMIF_BA[1:0]
EMIF_D[x:0]
EMIF_nDQM[x:0]
EMIF_A[x:0]
EMIF
EMIF Module Architecture
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SPNU563A–March 2018
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External Memory Interface (EMIF)
21.2.6 Asynchronous Controller and Interface
The EMIF easily interfaces to a variety of asynchronous devices including NOR Flash and SRAM. It can
be operated in two major modes (see Table 21-14):
• Normal Mode
• Select Strobe Mode
Table 21-14. Normal Mode vs. Select Strobe Mode
Mode Function of EMIF_nDQM pins Operation of EMIF_nCS[4:2]
Normal Mode Byte enables Active during the entire asynchronous access cycle
Select Strobe Mode Byte enables Active only during the strobe period of an access cycle
The first mode of operation is Normal Mode, in which the EMIF_nDQM pins of the EMIF function as byte
enables. In this mode, the EMIF_nCS[4:2] pins behaves as typical chip select signals, remaining active for
the duration of the asynchronous access. See Section 21.2.6.1 for an example interface with multiple 8-bit
devices.
The second mode of operation is Select Strobe Mode, in which the EMIF_nCS[4:2] pins act as a strobe,
active only during the strobe period of an access. In this mode, the EMIF_nDQM pins of the EMIF function
as standard byte enables for reads and writes. A summary of the differences between the two modes of
operation are shown in Table 21-14. Refer to Section 21.2.6.4 for the details of asynchronous operations
in Normal Mode, and to Section 21.2.6.5 for the details of asynchronous operations in Select Strobe
Mode. The EMIF hardware defaults to Normal Mode, but can be manually switched to Select Strobe Mode
by setting the SS bit in the asynchronous m (m = 1, 2, 3, or 4) configuration register (CEnCFG) (n = 2, 3,
or 4). Throughout the chapter, m can hold the values 1, 2, 3 or 4; and n can hold the values 2, 3, or 4.
The EMIF also provides configurable cycle timing parameters and an Extended Wait Mode that allows the
connected device to extend the strobe period of an access cycle. The following sections describe the
features related to interfacing with external asynchronous devices.
21.2.6.1 Interfacing to Asynchronous Memory
Figure 21-7 shows the EMIF's external pins used in interfacing with an asynchronous device. In
EMIF_nCS[n], n = 2, 3, or 4.
Figure 21-7. EMIF Asynchronous Interface
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