EMIF_nDQM[1:0]
DQ[15:0]
asynchronous
BE[1:0]
EMIF_nWE
EMIF_D[15:0]
EMIF_nCS[n]
EMIF
nWE
nCE
device
16−bit
EMIF_D[7:0]
EMIF_A[x:0]
EMIF_BA[1:0]
DQ[7:0]
A[(x+2):2]
A[1:0]
EMIF 8−bit
asynchronous
memory
a) EMIF to 8-bit memory interface
EMIF_D[15:0]
EMIF_A[x:0]
EMIF_BA[1]
DQ[15:0]
A[(x+1):1]
A[0]
EMIF 16−bit asynchronous
memory
b) EMIF to 16-bit memory interface
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EMIF Module Architecture
811
SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
External Memory Interface (EMIF)
Of special note is the connection between the EMIF and the external device's address bus. The EMIF
address pin EMIF_A[0] always provides the least significant bit of a 32-bit word address. Therefore, when
interfacing to a 16-bit or 8-bit asynchronous device, the EMIF_BA[1] and EMIF_BA[0] pins provide the
least-significant bits of the halfword or byte address, respectively. Additionally, when the EMIF interfaces
to a 16-bit asynchronous device, the EMIF_BA[0] pin can serve as the upper address line EMIF_A[22].
Figure 21-8 and Figure 21-9 show the mapping between the EMIF and the connected device's data and
address pins for various programmed data bus widths. The data bus width may be configured in the
asynchronous n configuration register (CEnCFG).
Figure 21-9 shows a common interface between the EMIF and external asynchronous memory. Figure 21-
9 shows an interface between the EMIF and an external memory with byte enables. The EMIF should be
operated in either Normal Mode or Select Strobe Mode when using this interface, so that the EMIF_nDQM
signals operate as byte enables.
Figure 21-8. EMIF to 8-bit/16-bit Memory Interface
Figure 21-9. Common Asynchronous Interface
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