CRC Control Registers
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SPNU563A–March 2018
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Cyclic Redundancy Check (CRC) Controller Module
18.4.1 CRC Global Control Register 0 (CRC_CTRL0)
Figure 18-9. CRC Global Control Register 0 (CRC_CTRL0) [offset = 00h]
31 16
Reserved
R-0
15 9 8
Reserved CH2_PSA_SWREST
R-0 R/W-0
7 1 0
Reserved CH1_PSA_SWREST
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-5. CRC Global Control Register 0 (CRC_CTRL0) Field Descriptions
Bit Field Value Description
31-9 Reserved 0 Reads return 0. Writes have no effect.
8 CH2_PSA_SWREST Channel 2 PSA Software Reset. When set, the PSA Signature Register is reset to all zero.
Software reset does not reset software reset bit itself. Therefore, CPU is required to clear
this bit by writing a 0.
0 PSA Signature Register is not reset.
1 PSA Signature Register is reset.
7-1 Reserved 0 Reads return 0. Writes have no effect.
0 CH1_PSA_SWREST Channel 1 PSA Software Reset. When set, the PSA Signature Register is reset to all zero.
Software reset does not reset software reset bit itself. Therefore, CPU is required to clear
this bit by writing a 0.
0 PSA Signature Register is not reset.
1 PSA Signature Register is reset.
18.4.2 CRC Global Control Register (CRC_CTRL1)
Figure 18-10. CRC Global Control Register 1 (CRC_CTRL1) [offset = 08h]
31 16
Reserved
R-0
15 1 0
Reserved PWDN
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-6. CRC Global Control Register 1 (CRC_CTRL1) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Reads return 0. Writes have no effect.
0 PWDN Power Down. When set, CRC module is put in power-down mode.
0 CRC is not in power-down mode.
1 CRC is in power-down mode.