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DCC Control Registers
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SPNU563A–March 2018
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Dual-Clock Comparator (DCC) Module
15.4 DCC Control Registers
This section describes the dual-clock comparator (DCC) module control and status registers. The registers
support 8-bit, 16-bit or 32-bit writes and are aligned on a word (32-bit) boundary. Table 15-1 shows
address offsets from the module base address. The base address for the control registers is FFFF EC00h
for DCC1 and FFFF F400h for DCC2.
Table 15-1. DCC Control Registers
Offset Acronym Register Description Section
00h DCCGCTRL DCC Global Control Register Section 15.4.1
04h DCCREV DCC Revision Id Register Section 15.4.2
08h DCCCNT0SEED DCC Counter0 Seed Register Section 15.4.3
0Ch DCCVALID0SEED DCC Valid0 Seed Register Section 15.4.4
10h DCCCNT1SEED DCC Counter1 Seed Register Section 15.4.5
14h DCCSTAT DCC Status Register Section 15.4.6
18h DCCCNT0 DCC Counter0 Value Register Section 15.4.7
1Ch DCCVALID0 DCC Valid0 Value Register Section 15.4.8
20h DCCCNT1 DCC Counter1 Value Register Section 15.4.9
24h DCCCNT1CLKSRC DCC Counter1 Clock Source Selection Register Section 15.4.10
28h DCCCNT0CLKSRC DCC Counter0 Clock Source Selection Register Section 15.4.11
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