Texas Instruments TMS570LC4357

PBIST Control Registers www.ti.com
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SPNU563A–March 2018
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Programmable Built-In Self-Test (PBIST) Module
9.5.8 Fail Status Address Registers (FSRA0 and FSRA1)
These registers capture the memory address of the first failure on port 0 and port 1, respectively. Figure 9-
11 and Table 9-10 illustrate the FSRA0 register, while Figure 9-12 and Table 9-11 illustrate the FSRA1
register.
Figure 9-11. Fail Status Address Register 0 (FSRA0) [offset = 01A0h]
31 16
Reserved
R-0
15 0
FSRA0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-10. Fail Status Address Register 0 (FSRA0) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reads return 0. Writes have no effect.
15-0 FSRA0 Fail Status Address 0. Contains the address of the first failure.
Figure 9-12. Fail Status Address Register 1 (FSRA1) [offset = 01A4h]
31 16
Reserved
R-0
15 0
FSRA1
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-11. Fail Status Address Register 1 (FSRA1) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reads return 0. Writes have no effect.
15-0 FSRA1 Fail Status Address 1. Contains the address of the first failure.