SDC MMR Registers
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SPNU563A–March 2018
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4.4 SDC MMR Registers
Table 4-5 lists the Safety Diagnostic Checker registers. The registers support only 32-bit reads. The offset
is relative to the base address. The base address for the registers is FA00 0000h.
Table 4-5. SDC MMR Registers
Offset Acronym Register Description Section
0h SDC_STATUS SDC Status Register Section 4.4.1
4h SDC_CONTROL SDC Control Register Section 4.4.2
8h ERR_GENERIC_PARITY Error Generic Parity Register Section 4.4.3
Ch ERR_UNEXPECTED_TRANS Error Unexpected Transaction Register Section 4.4.4
10h ERR_TRANS_ID Error Transaction ID Register Section 4.4.5
14h ERR_TRANS_SIGNATURE Error Transaction Signature Register Section 4.4.6
18h ERR_TRANS_TYPE Error Transaction Type Register Section 4.4.7
1Ch ERR_USER_PARITY Error User Parity Register Section 4.4.8
20h SERR_UNEXPECTED_MID Slave Error Unexpected Master ID register Section 4.4.9
24h SERR_ADDR_DECODE Slave Error Address Decode Register Section 4.4.10
28h SERR_USER_PARITY Slave Error User Parity Register Section 4.4.11
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