HWAG Registers
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SPNU563A–March 2018
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High-End Timer (N2HET) Module
23.5.5 HWAG Interrupt Enable Set Register (HWAENASET)
Figure 23-93. HWAG Interrupt Enable Set Register (HWAENASET)
31 8
Reserved
R-0
7 6 5 4 3 2 1 0
SETINTENA7 SETINTENA6 SETINTENA5 SETINTENA4 SETINTENA3 SETINTENA2 SETINTENA1 SETINTENA0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-56. HWAG Interrupt Enable Set Register (HWAENASET) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reads return 0. Writes have no effect.
7-0 SETINTENA[n] Enable interrupt. See Table 23-57.
0 Read: Corresponding interrupt is not enabled.
Write: No effect.
1 Read: Corresponding interrupt is enabled.
Write: Enable corresponding interrupt.
Table 23-57. HWAG Interrupts
Bit Interrupt
0 Overflow period
1 Singularity not found
2 Tooth interrupt
3 ACNT overflow
4 PCNT(n) > 2 x PCNT (n-1) during normal tooth
5 Bad active edge tooth
6 Gap flag
7 Angle increment overflow
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