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System and Peripheral Control Registers
205
SPNU563A–March 2018
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Architecture
2.5.2 Secondary System Control Registers (SYS2)
This section describes the secondary frame of system registers. The start address of the secondary
system module frame is FFFF E100h. The registers support 8-, 16-, and 32-bit writes. The offset is relative
to the system module frame start address.
Table 2-71 contains a list of the secondary system control registers.
NOTE: All additional registers in the secondary system frame are reserved.
Table 2-71. Secondary System Control Registers
Offset Acronym Register Description Section
00h PLLCTL3 PLL Control Register 3 Section 2.5.2.1
08h STCLKDIV CPU Logic BIST Clock Divider Section 2.5.2.2
24h ECPCNTL ECP Control Register. The ECPCNTL register has the mirrored
location at this address.
Section 2.5.1.43
28h ECPCNTL1 ECP Control Register 1. Section 2.5.2.3
3Ch CLK2CNTRL Clock 2 Control Register Section 2.5.2.4
40h VCLKACON1 Peripheral Asynchronous Clock Configuration 1 Register Section 2.5.2.5
54h HCLKCNTL HCLK Control Register Section 2.5.2.6
70h CLKSLIP Clock Slip Control Register Section 2.5.2.7
78h IP1ECCERREN IP ECC Error Enable Register Section 2.5.2.8
ECh EFC_CTLREG EFUSE Controller Control Register Section 2.5.2.9
F0h DIEIDL_REG0 Die Identification Register Lower Word Section 2.5.2.10
F4h DIEIDH_REG1 Die Identification Register Upper Word Section 2.5.2.11
F8h DIEIDL_REG2 Die Identification Register Lower Word Section 2.5.2.12
FCh DIEIDH_REG3 Die Identification Register Upper Word Section 2.5.2.13
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