Texas Instruments TMS570LC4357

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System and Peripheral Control Registers www.ti.com
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SPNU563A–March 2018
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Architecture
2.5.1.43 ECP Control Register (ECPCNTL)
The ECP register, shown in Figure 2-50 and described in Table 2-62, configures the ECLK pin in
functional mode.
NOTE: ECLK Functional mode configuration.
The ECLK pin must be placed into Functional mode by setting the ECPCLKFUN bit to 1 in
the SYSPC1 register before a clock source will be visible on the ECLK pin.
Figure 2-50. ECP Control Register (ECPCNTL) (offset = D4h)
31 25 24 23 22 18 17 16
Reserved ECPSSEL ECPCOS Reserved Reserved
R-0 R/W-0 R/W-0 R-0 R/W-0
15 0
ECPDIV
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-62. ECP Control Register (ECPCNTL) Field Descriptions
Bit Field Value Description
31-25 Reserved 0 Reads return 0. Writes have no effect.
24 ECPSSEL This bit allows the selection between VCLK and OSCIN as the clock source for ECLK.
Note: Other ECLK clock sources are available for debug purposes by configuring the
CLKTEST register.
0 VCLK is selected as the ECP clock source.
1 OSCIN is selected as the ECP clock source.
23 ECPCOS ECP continue on suspend.
Note: Suspend mode is entered while performing certain JTAG debugging operations.
0 ECLK output is disabled in suspend mode. ECLK output will be shut off and will not be seen on
the I/O pin of the device.
1 ECLK output is not disabled in suspend mode. ECLK output will not be shut off and will be seen
on the I/O pin of the device.
22-18 Reserved 0 Reads return 0. Writes have no effect.
17-16 Reserved 0 Reads return 0 or 1 depends on what is written. The functionality of this bit is unavailable in this
device.
15-0 ECPDIV 0-FFFFh ECP divider value. The value of ECPDIV bits determine the external clock (ECP clock) frequency
as a ratio of VBUS clock or OSCIN as shown in the formula: