Texas Instruments TMS570LC4357

N2HET Control Registers www.ti.com
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SPNU563A–March 2018
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High-End Timer (N2HET) Module
23.4.15 Request Enable Set Register (HETREQENS)
N2HET1: offset = FFF7 B83Ch; N2HET2: offset = FFF7 B93Ch
Figure 23-70. Request Enable Set Register (HETREQENS)
31 8
Reserved
R-0
7 6 5 4 3 2 1 0
REQENA7 REQENA6 REQENA5 REQENA4 REQENA3 REQENA2 REQENA1 REQENA0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-31. Request Enable Set Register (HETREQENS) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reads return 0. Writes have no effect.
7-0 REQENAn Request Enable Bits
0 Read: Returns the information that request line n is disabled.
Write: Writing a 0 has no effect.
1 Read: Returns the information that request line n is enabled.
Write: Writing a 1 to bit n enables the N2HET request line n.
Note: The request line can trigger a DMA control packet (DMA channel), an HTU double control
packet (DCP) or both simultaneously. The HETREQDS register determines to which module(s) the
N2HET request line n is assigned.
Note: A disabled request line does not memorize old requests. So there are no pending requests to
service after enabling request line n.
23.4.16 Request Enable Clear Register (HETREQENC)
N2HET1: offset = FFF7 B840h; N2HET2: offset = FFF7 B940h
Figure 23-71. Request Enable Clear Register (HETREQENC)
31 8
Reserved
R-0
7 6 5 4 3 2 1 0
REQDIS7 REQDIS6 REQDIS5 REQDIS4 REQDIS3 REQDIS2 REQDIS1 REQDIS0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23-32. Request Enable Clear Register (HETREQENC) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reads return 0. Writes have no effect.
7-0 REQDISn Request Disable Bits
0 Read: Returns the information that request line n is disabled.
Write: Writing a 0 has no effect.
1 Read: Returns the information that request line n is enabled.
Write: Writing a 1 to bit n disables the N2HET request line n.